A Novel Low-Power Shift-Register Controller for Digital Low-Dropout Regulators

This paper introduces a low-power controller circuit for improving the digital low-dropout regulator's (DLDO) current efficiency by reducing the quiescent current during both steady and transient states. The proposed controller forces the right shift operation to turn on/off the pMOSFET switches under the influence of the output voltage variation, and the proposed control mechanism prevents the unnecessary switching of the intermediate nodes in the controller at each clock edge to reduce the quiescent current. With a 4-bit DLDO integrated with the proposed S/R controller, designed and simulated in a 65nm CMOS process, we achieve a significant reduction in quiescent current as compared to the standard SIR controller-based DLDO. The designed DLDO integrated with the proposed S/R controller operating at 100MHz clock frequency performed 0.45V output regulation with 98.85% current efficiency and 2.3
$\mu \mathrm{A}$
quiescent current. Also, the quiescent current for the proposed design is reduced by more than 40% for DLDO operating at higher clock frequency or having a bigger pMOSFET array when compared with the standard design; the layout dimension of the proposed S/R controller with a 4-bit pMOSFET array is 25.5
$\mu\mathrm{m}$
x 30.93
$\mu\mathrm{m}$
. The robustness of the design for mismatches and process variations is verified via simulations, which indicates the excellent energy efficiency of the proposed low-power controller.