ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications

We propose an Adaptive Body Biasing (ABB) assisted method for the improvement in resolution and reduction in on-chip area of time-to-digital converter (TDC). The proposed method also improves the metastability window with reduced hold time while maintaining the setup time same as conventional architecture of True Single-Phase Clock (TSPC) D flip flops (DFFs). In this article, we use Positive Edge Triggered (PET) TSPC DFFs for our analysis, which exhibit a significant hold time but benefit from a zero-setup time. Further, with the application of ABB, the desired delay difference between the delay lines of Vernier TDCs is achieved without having any area overhead. The simulation work is carried out using a 28 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology node of STMicroelectronics (STM) at a voltage supply (V
DD
) of 0.6 V.