An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range

The paper presents a L1 cache SRAM design using 3nm FinFET technology, achieving 4.5GHz frequency and wide-range DVFS operation. It proposes an innovative write circuit to overcome writability issues at low voltages (0.45v) and higher voltages (1.1v). The methods are implemented in a 3nm FinFET SRAM. Silicon shmoo plot validates the achievement of the targeted VMIN and frequency in the design.