A 95-nA Quiescent-Current Fast-Transient Output-Capacitor-Less LDO with Enhanced Load Regulation for IoT Applications

An ultra-low quiescent output-capacitor-less low-dropout regulator (OCL- LDO) with enhanced load regulation is proposed for Internet-of-Things (IoT) devices. The proposed LDO architecture is based on a flipped-voltage-follower topology where the Gm stage with current mirror load replaces the constant current source of the folded-cascode common gate amplifier to improve the DC load regulation and transient performance. A super source follower (SSF), which acts as a voltage buffer, is inserted to drive the large power transistor. Further, a dynamic sensing unit is utilized to achieve a fast settling time during a low-to-high load step. In a 65 nm low-power CMOS process, the proposed LDO was designed. The LDO consumes 95
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A quiescent current and can deliver up to 50 mA load current with a 1.2 V supply and 1 V regulated output. It achieves a DC load regulation of 14.8 mV/A by varying the load current from 500 nA to 50 mA. With a 100 pF load capacitor, the output voltage undershoot with a 100 ns rise time is 626 mV and reduces to 530 mV with a 200 ns rise time for a full load step current and settles within 350 ns.