Measurement of Circuit Parasitics of a 200kW SiC based Stack

Converters with high power density are becoming necessary in applications such as traction inverters and electric vehicles, where the inverter stage must process power in the range of a few hundred kilowatts. As the inverters are often hard-switched, SiC power modules can enable high power density due to superior switching, conduction loss, and thermal performance. However, due to the fast switching transients of SiC MOSFETs, circuit parasitics can significantly impact the switching dynamics resulting in prolonged oscillation, high device stress, and crosstalk and EMI-related issues. So, estimation of circuit parasitic is essential for optimal gate and power circuit layout design. The experimental measurement-based parasitic estimation technique is superior to the electromagnetic simulation-based approach when the internal geometry of the power module is unknown. This paper presents a systematic approach to estimating parasitic inductances of a 200 kW SiC-based stack. The accuracy of this proposed method is verified through experiment and electromagnetic simulation with the help of ANSYS Q3D Extractor.