Common-Mode Voltage in Three-Level T-Type Inverter: Modeling, Analysis, and Compensation

This paper investigates the origins of common-mode voltage (CMV) noises in SiC MOSFET-based three-level T-type inverters (3LT
²
I), targeting adjustable speed drive (ASD) systems, and proposes methods for their mitigation. Although achieving zero common-mode voltage (ZCMV) is theoretically unattainable in a two-level voltage source inverter (2L-VSI), it can be realized in a 3LT
²
I by selecting specific switching states. However, the necessary simultaneous switching of two half-bridges in ZCMV methods generates significant CMV noises, which are due to the dead-time and differences in output voltage transition times. This work proposes a method to mitigate these CMV noises through precisely adjusting the timing of the transitions in the gate drive signals. This method can reduce electromagnetic interference (EMI) associated with CMV and minimize passive filter size. Lastly, the paper answers the critical question: Is full CMV suppression practically possible?