PCB Layout Design Impact on Three Level Buck Converters for USB3.1 PD Application

In this paper, a three-level buck converter (TLBC) is analyzed for use as a USB 3.1 high-power PD application. The performance of the circuit is simulated by incorporating estimated parasitic inductances based on the layout of the designed 4-layer PCB. The PCB layout is further optimized to reduce the parasitic trace inductance by intentionally designing a vertical power loop. Each PCB trace inductance for the smallest power loop design is quantitatively analyzed by the deployment of different PCB layout approaches through the use of Ansys Q3D software. The turn-off voltage spikes for the TLBC are simulated both with and without the optimized PCB trace inductance. Finally, a 240W prototype with the optimized PCB layout is built to demonstrate a higher efficiency and lower voltage spike for TLBCs.