A 3-level Active Gate Driver Network for SiC MOSFETs to Minimize Overshoot and Switching Losses

Active gate drivers for wide-bandgap devices are designed to reduce current overshoot and parasitic ringing caused by high dv/dt and di/dt transients while enabling high switching speeds to reduce switching losses. This work presents a 3-level Active Gate Driver (3L-AGD) network that changes the gate resistance during the switching transient without the need for a μC or an FPGA to control active devices to adjust the switching slew rate. Optimal operating conditions for the 3L-AGD are developed to minimize current peaks and energy losses. In the double-pulse test, the operating principle of the 3L-AGD is confirmed and the reduced turn-on energy losses are determined to be 5 %-30 % less with equal or lower current overshoots compared to a conventional gate driver.