Development of Pressure Contact Technology for Multi-chip SiC Modules with Low Parasitics

Conventional packaging limits the full exploitation of the high-frequency and high-power density capabilities of silicon-carbide (SiC) metal-semiconductor-oxide field-effect transistors. This work reports a pressure contact packaging technology on SiC modules to replace weak bonding elements and to achieve double-sided cooling. Three viable module layouts for a half bridge with multiple parallel chips are proposed, focusing on maximum power density and functional performance. A novel spring connector is designed to accommodate the small pad size and achieve pressure contacts on the chips. The path for the gate loop and power loop are optimized to ensure a balanced current distribution. The parasitic inductance of the experimental prototype with bus bars is only 4.76 nH, facilitating a high switching speed. The feasibility of the proposed packaging approach is confirmed by both extensive simulations and experiments.