A 60-GHz Phase-Locked Loop Using Standing- Wave Oscillator for Clock Distribution in 2-D Phased-Array

This letter presents a 60-GHz analog phase-locked loop (PLL) incorporating a half-wavelength standing-wave oscillator (SWO) as part of the clock distribution network in a sub-THz 2-D phased-array transceiver. The frequency is selected as one-fourth of the target carrier frequency to comply with the 625-
$\mu \text{m}$
half- wavelength element spacing requirement while facilitating array scaling. The PLL features a sampler-based phase detector (PD) and retiming flip-flop at the divider chain output to ensure minimal noise injection. Fabricated in TSMC 28-nm CMOS, the measurement results show an integrated jitter of 87.5 fsec from 1 kHz to 100 MHz. Consuming 31.35 mW of power, the presented PLL achieves a figure-of-merit of -270 dB.