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A 16 384-bit dynamic RAM | IEEE Journals & Magazine | IEEE Xplore

Abstract:

A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /s...Show More

Abstract:

A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /spl mu/m/SUP 2/. The device is fabricated in n-channel two-layer polysilicon gate technology using conventional design rules. The chip size is 145 by 234 mils. A low-power sense amplifier is used for each 64 memory cells. A special refresh mode is possible in which all 256 sense amplifiers are active, and the entire memory can be refreshed in 64 address cycles.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 11, Issue: 5, October 1976)
Page(s): 570 - 574
Date of Publication: 31 October 1976

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