A 1.5V 500MHz Fully Differential CMOS Sample and Hold Circuit Using Double Sampling

This paper proposes a design of a 1.5-V 500-MHz fully-differential CMOS sample-and-hold (S/H) circuit using double-sampling for ADCs. In contrast to a traditional closed-loop S/H circuit, a double-sampled S/H circuit improves the sampling rate and enhances dynamic performance while pre-serving competitive power consumption. Besides, the employment of improved bootstrapped and opamp circuits achieves high and almost constant linearity in low-voltage and high-speed operation. The sample and hold circuit is implemented using TSMC 0.18 µm CMOS technology. The measurements indicate that the proposed S/H circuit can achieve a sampling rate of 500MS/s in a maximum 140MHz 0.8Vpp input sinewave signal with total harmonic distortion lower than -62dB, linearity exceeding 10 effective bits, and a power dissipation of 5.6mw @ 1.5V.