Robustness-Improved ESD Protection Devices With Low Leakage Using Middle Silicon Layer in Double SOI Technology

A novel implementation for electrostatic discharge (ESD) protection is demonstrated, which involves two structures named MOSFET in parallel with diode (MOS-DIO) and MOSFET in parallel with silicon-controlled rectifier (MOS-SCR). The fabricated structures exhibit enhanced robustness enabled through the double silicon-on-insulator (DSOI) technology. The implementation combines a MOSFET in the top silicon film with a diode or a silicon-controlled rectifier (SCR) located in the middle silicon layer. Transmission line pulse (TLP) experiments show that compared with the traditional single nMOS structure, both DSOI MOS-DIO and MOS-SCR exhibit superior current discharge capability with an increase in failure current of up to 39% under the same footprint. The leakage of the proposed structures is also reduced to below 0.2 pA/
$\mu$
m thanks to the double buried oxide isolation. In addition, both triggering and holding voltages can be flexibly tuned via the positioning of the two shunt devices. Technology computer-aided design (TCAD) simulations were carried out for MOS-SCR to interpret the physical mechanism and predict the performance under different device parameters, including gate length, stacked modes, and ambient temperature.