Low-Cost FPGA Implementation of Deep Learning-Based Heart Sound Segmentation for Real-Time CVDs Screening

The development of real-time, reliable, low-cost automatic phonocardiogram (PCG) analysis systems is critical for the early detection of cardiovascular diseases (CVDs), especially in countries with limited access to primary health care programs. Once the raw PCG acquired by the stethoscope has been preprocessed, the first key task is its segmentation into the fundamental heart sounds. For this purpose, an optimized hardware implementation of the segmentation algorithm is essential to attain a computer-aided diagnostic system based on PCGs. This article presents the optimization of a U-Net-based segmentation algorithm for its implementation in a low-end field-programmable gate array (FPGA) using low-resolution fixed-point data types. The optimization strategies seek to reduce the system latency while maintaining a constrained consumption of FPGA resources, aiming for a real-time response from the stethoscope data acquisition to the CVD detection. Experimental results prove a 64% decrease in latency compared to a baseline version, a 3.9% reduction of block random access memory (BRAM), which is the limiting resource of the design, and a 70% reduction in energy consumption. To the best of our knowledge, this is the first work to exhaustively study different optimization strategies for implementing a large 1-D U-Net-based model, achieving real-time fully characterized performance.