A 10 kV SiC MOSFET Power Module With Optimized System Interface and Electric Field Distribution

This article introduces a holistic and systematic design methodology tailored to the 10 kV silicon carbide (SiC) mosfet power modules. Multiobjective optimization was achieved with enhanced electric-field (E-field) distribution, minimized common-mode (CM) parasitic capacitance, and reduced system-level parasitic inductances. The proposed approach encompasses two innovative techniques: 1) an electric-potential-oriented module-system interface to reduce system-level parasitic inductance while maximizing insulation capability; 2) stacked substrates with patterned middle layer copper to alleviate the E-field concentration at the triple-point and reduce the maximum E-field without compromising on thermal resistance. The effectiveness of these innovative approaches is substantiated through the development of a 10 kV SiC mosfet power module. The optimized layout presents well-balanced 5.6 nH power loop inductance with embedded decoupling capacitors and record-low 28 pF CM parasitic capacitance, attributed to the middle layer pattern structure. In addition, a 38.6% E-field concentration reduction at the triple-point is identified compared to conventional stacked substrates. Experimental validation showcases its robust voltage insulation capability with a leakage current of 0.87 μA at 10 kV, a 33 kV dc, and 25 kV ac surface flashover for worst-case system fault conditions. The partial discharge inception voltage of the proposed middle layer patterned stacked substrates is verified at 16.8 kVrms. Dynamic performance validation through a double-pulse test at 5 kV showcases negligible ringing and voltage overshoot. All these exceptional attributes position the packaged 10 kV SiC mosfet power module as an exemplary choice for MV power electronics applications.