A Design Framework for Neural Network Architecture Exploration

The use of neural networks (NNs) has significantly increased due to their ability to solve complex problems in different domains. NNs are increasingly being employed in embedded applications, so energy-efficient solutions are critical to enabling the wide adoption of such technologies. However, the flexibility of NNs makes the design of accelerators quite challenging, as there are many architectural parameters that must be optimized for each case, such as the number of inputs, input width, number of pipeline stages, activation functions, etc. This work proposes a framework that provides an automatic generation of RTL descriptions of NN architectures to expedite design space exploration. To show the usefulness of our solution, we compare several NN models in terms of important design parameters such as area and power, along with a model accuracy performance. Special attention should be given to carefully managing the bit width. Additionally, when prioritizing model accuracy, careful consideration of the bit width and the number of hidden layers is essential, as hidden layers may contribute to propagated errors.