Extending Multilevel ALS to Design ATMRs

As transistors shrink to nanoscale dimensions, their susceptibility to faults increases. The Approximate Triple Modu-lar Redundancy (ATMR) technique utilizes approximate versions of a circuit connected to a voter to mitigate these faults. ATMR aims to enhance a circuit's fault tolerance while avoiding the threefold area increase associated with traditional TMR. This work introduces the first extension of a multilevel Approximate Logic Synthesis tool for ATMR construction. Leveraging a multilevel ALS approach to generate ATMR modules allows integrating advancements from the ALS domain into ATMR development. Experimental results generate ATMR designs with comparable quality to the state-of-the-art dedicated approach.