VLSI Implementation of an Annealing Accelerator for Solving Combinatorial Optimization Problems

Although quantum computing is expected to supplant traditional computing in several application fields, its adoption is hampered by temperature and economic constraints. To overcome these hurdles, researchers have proposed complementary metal-oxide-semiconductor (CMOS) annealing circuits. These circuits draw inspiration from quantum computing algorithms such as quantum annealing and aim to achieve near-quantum benefits by leveraging traditional CMOS technologies. This paper introduces an Ising-model-based hardware architecture that can be applied to combinatorial optimization problems (COPs). With its ability to express quadratic unconstrained binary optimization (QUBO) formulations as polynomials, the Ising model facilitates the encapsulation of multiple solutions and mapping onto fully connected architecture. The proposed annealing accelerator utilizes traditional circuit technologies, including pseudo-random number generators (PRNGs), to realize the required algorithms. The chip proposed herein, implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology, operates at 50 MHz and covers an area of $3.24{\mathrm{m}}{{\mathrm{m}}^2}$3.24mm2. Experimental results demonstrate the excellent performance of this annealing accelerator in terms of area and power consumption, indicating its promise for use in solving COPs rapidly.