Design Implementation of FPGA-Based Neural Network Acceleration

Currently, convolutional neural networks have achieved significant applications in the field of computer vision, including image classification and object detection. However, many practical applications require low latency and low power consumption during the forward inference stage. To address this issue, we employed a series of optimization strategies such as parameter reordering and multi-channel data transfer to design and implement a convolutional neural network accelerator architecture based on FPGA. Taking the YOLOv5 object detection algorithm as an example, we provide a detailed overview of the process of mapping the convolutional neural network model to FPGA. In-depth analysis and modeling of accelerator performance and resource consumption were conducted, taking into account the actual transmission delay, thereby reducing the error between theoretical and actual accelerator latency. We also made improvements to the input and output modules in the accelerator architecture, effectively increasing the practical utilization of bus bandwidth. The experimental results show that a performance of 30.15 GOP/s is obtained on zynq7020, which is 71.4 times more energy-efficient and 7.3 times more performant compared to AMD5900HX CPUs, and 86 times more energy-efficient and 112.9 times more performant compared to dual-core ARM-A9 CPUs.