An Investigative Study on Performance and Reliability Effects on S2C/TSPC/SCD D-Flip-Flops using 16 nm CMOS Process

The D-flip-flop functions as an electronic memory unit due to its ability to maintain a consistent output unless intentionally modified by adjusting the state of the D input and subsequent application of a rising clock signal. In this study, we investigated the performance, reliability, and supply scalability of S2C/TSPC/SCD D-Flip-Flop using 16nm CMOS technology. The S2CFF showcased a decrease in the delay of 87.29%/85.56% at 27°C/107°C as the power supply is swept from 0.7V-1.2V and power consumption with an increase of 90.35%/89.79% at the temperature points of 27°C and 107°C as the VDD is scaled up from 0.7V to 1.2V. In TSPCFF as the VDD is increased from 0.7 to 1.2V the performance of delay and power consumption is decreased and increased respectively. At 27°C/107°C the delay is decreased by 57.76%/89.78% and power consumption is increased by 89.78%/88.57%. The same format is followed by the SCDFF with a decrease and increase in delay and power consumption respectively as the voltage is raised from 0.7V to 1.2V. At 27°C/107°C the delay is decreased by 94.37%/58.65% and an increase in power by 93.23% /93.67%. The D-flip-flops are the indirect blocks of building the global technology of Artificial Intelligence (AI) which includes the digital circuitry of neural networks, hardware architectures, data processing, AI computations, and machine models. Along with that, the D-Flip-Flops play a major part in registers, counters, and synchronous digital circuits.