A design method for the multi-operand adder in logic synthesis flow

In order to improve the performance and reduce the delay of multi-operand adder in logic synthesis flow, a multi-operand adder design method based on adaptive CSA is proposed in this paper. The method uses Wallace Tree to achieve low latency multi-operand adder design. Moreover, an adaptive approach is used to improve the CSA part of the Wallace Tree to further reduce the delay. In this paper, the method is applied to achieve a multi-operand adder design by logically synthesizing the input-specific adder design using the smic28nm process library as the target library. Analysis of its performance shows that the methodology can further reduce the latency and on top of that area and power.