Energy Efficient Vedic Multiplier

A multiplier is an essential component of every computer or processor. In most cases, the multiplications executed per unit time are used to estimate the performance of microcontrollers and digital signal processors. As a result, a more advanced multiplier architecture is being developed to boost system efficiency. The Vedic multiplier is a viable option. Its straightforward architecture and increased speed make it an unbeatable combination for completing complex multiplication calculations. These characteristics prove that the Vedic multiplier using hybrid logic implementation further reduces power consumption and increases speed, which is an essential limitation in embedded systems. In this work, we introduce a Vedic multiplier named "Urdhva Tiryakbhayam" which means "vertical and horizontal" multiplier and is realized by using a hybrid logic adder, which is the first of its kind. The multiplier can be used for Fast Fourier Transform (FFT) and other digital signal processing (DSP) applications, such as image processing, software-defined radio, and wireless communications. Urdhva Tiryakbhyam Sutra is widely discussed in various search articles and proved the most effective method (algorithm), providing the smallest delay for multiplications of various sizes. In addition, the Urdhva tiryakbhyam Sutra circuit, which uses a hybrid logic full adder for 4x4 bit multiplication, is implemented, and simulated in the Cadence Virtuoso environment using 180 nm CMOS technology.