β-Ga2O3 Based Bulk-Planar Junctionless Transistor for Superior Electrostatic Integrity at Sub-7nm Technology

In this work, we propose a bulk-planar junctionless transistor using β-Ga
2
O
3
as device layer material (β-Ga
2
O
3
-BPJLT) downscaled till 7nm and compared it with conventional Silicon-channel bulk-planar junctionless transistor (Si-BPJLT) through TCAD simulations. The proposed device exhibits better subthreshold performance than Si-BPJLT. Due to shorter bond length and lower permittivity of gallium oxide, increased volume depletion presents an idea of improved scalability with enhanced electrostatic integrity. Moreover, the highly penetrating drain field in device layer compensates reduced mobility to achieve comparable drift velocity. Relaxation in metal-gate work function is obtained using substrate bias and substrate doping in bulk-planar architecture to control the carriers. Furthermore, with the application of high-κ spacers, fringing field realizes higher source/channel barrier with larger effective channel length resulting in reduced drain-induced-barrier lowering and hence the leakage current (I
OFF
~10
^-13
). Additionally, beyond flatband voltage due to stronger accumulation through spacers, reduced parasitic resistance provides better subthreshold swing (SS) along with improved drive current.