Small-size low-power bipolar memory cell

A d.c.-stable random-access memory (RAM) cell employing n-p-n and p-n-p transistors has been designed in a concurrent circuit-layout approach. Test chips with 2×3 arrays have been processed in a standard bipolar technology. Due to the merging of devices, the area required for a cell is only 14 mil
²
. The cells have been operated at an extremely low d.c. standby power of less than 0.1 μW/cell. In spite of this low standby power, an array access time of 10 ns has been measured on a simulated 512-bit array in a pulsed power mode.