UVM-Based Design and Verification of AHB-Lite to AXI Bridge

Over the last few decades, chip designing has evolved and become complex across several diverse areas, leading to increased verification time and effort. A longer verification process delays the completion of a design and sets back the time-to-market target. Universal Verification Methodology (UVM) provides flexible and reusable verification components that help us verify at the highest level and reduce verification time. Therefore, the proposed work is an implementation of an AHB-Lite to AXI bridge protocol and a UVM-based model that can fully verify the design. System-on-chip (SoC) designs widely use Advanced Microcontroller Bus Architecture (AMBA) standards for interconnections and implement a variety of buses to communicate with Intellectual Properties (IP). These designs can quickly become complex as more IPs are added to the SoC. Using Xilinx Vivado v2023.1, we successfully implemented a synthesizable bridge design and UVM testbench. We achieved 100% functional coverage and up to 98.75% code coverage.