Low Power and Area Efficient Borrow Select Subtractor

The fundamental circuit modules in the architecture of processors, adders and subtractors, are what give processors their speed. The number of bits in the operands, which in turn affects the LSB to MSB sequential borrow bit propagation, limits the processing speed of subtraction. This Work provides improved borrow select subtractor architectures with higher area efficiency and lower power consumption. The alterations made in the logical sequence flow of the subtraction process by using blocks with fewer logic gates result in fewer gates, which leads to fewer devices, a smaller footprint, and less power dissipation. Utilizing simulations from Xilinx ISE 14.7 on the UMC 90nm technology library, architectures have been verified. Comparing the proposed methodologies to existing designs serves to highlight their comparative advantages. The area occupied less by 17.94%, but the delay slightly increases by 18.8% for EBSS with RHBS when compared with EBSS with BLO.