A Double-Edge Triggered Asynchronous Gray Counter for Use as a Coarse Counter in VCO ADCs

This brief presents an asynchronous double-edge triggered Gray counter that can advantageously be used as coarse counter in a coarse-fine VCO ADC. We show that, in spite of using only a single counter and a single sampling register, it is possible to resolve the ambiguity in the coarse counter value caused by metastability and delay. We present simple decoding logic that performs both Gray-to-binary conversion and ambiguity resolution. A comparative case study is made for an 11 bit coarse-fine architecture based on the new Gray counter and a prior-art double-sampling binary counter. A reduction of 21% in area has been obtained, while at the same time post-layout simulations show a power saving of 17.5%.