All-Digital Time Register Based On Recursive Delay-Line

This work proposes an all-digital time register suitable for time-mode signal processing which employs only standard digital cells. The operation principle is based on the use of a delay line in a feedback loop topology. The main benefit of the proposed time register is the independency of the full-scale input range by the length of the delay-line. The proposed circuit was designed and simulated using TSMC 65nm CMOS process. Operating at 50MHz sampling frequency the worst-case time registration error was 15ps for a full-scale input of 5ns.