A high-speed autozeroing comparator with reduced current consumption

A comparator based on autozeroing technique with reduced power consumption for high-speed and high-resolution applications is proposed in this paper. The overall comparator topology is based on a cascade connection of differential amplifiers and one latch comparator. Due to its high sensitivity, it is suitable to be employed in high-resolution analog to digital converters and sampling rates up to 50Msps. The differential input voltage resolution is equal to 400 μVpp. The circuit is designed using a CMOS 65 nm technology node. Following a power switching technique, the current consumption of amplification stages can be reduced up to 30%, without affecting the overall performance of the comparator.