Netlist Compaction IR Drop Simulation Flow for Mixed Signal Power Integrity Analysis

In this work, a novel netlist compaction methodology was proposed and exploited as to speed-up the power integrity simulations of mixed signal SoC. The proposed methodology surpasses the time-domain non-linear simulations by introducing small-signal linear approximation approaches, thus accelerating the IR drop simulation procedure. As a digital cell, two ring-oscillators, oscillating at different frequencies, were implemented as the basic digital logic cell, using a 22 nm FDSOI CMOS process and, for simulation purposes, an array of digital cells was synthesized. In the top-level simulation scheme, both PCB and package models were included along with the PDN parasitics, as to improve the accuracy of the simulation. The presented methodology provides a significant netlist compaction technique while enabling power integrity simulations in large-scale digital circuits.