Asymmetric and Double-Layered Gate-All- Around Structures of 1T-DRAM for Sensing Margin and Retention Improvement

A general dynamic random access memory (DRAM) is consisted of transistor and capacitor and has continuously scaled down the cell size for larger memory density. However, one transistor-DRAM (1T-DRAM) is a promising device, which integrates both transistor and capacitor into one transistor. In this article, 1T-DRAM is a gate-all-around (GAA) structure, and silicon germanium (SiGe) and silicon were used as body and source/drain to form a quantum well in the valence band. The performance of 1T-DRAM is decided with sensing margin and retention. Expanding the capacity of the quantum well and lowering the recombination rate in the body are desired. Therefore, three body structures are proposed to improve the performance of the 1T-DRAM while maintaining its cell size. First, asymmetric structure is proposed to decrease the recombination rate at the underlap region between the body and source by lowering the mole fraction. Since the recombination relieves as the mole fraction decreases, it is possible to improve the retention by lowering the mole fraction. In addition, the double-layered structure is designed to increase the capacity of the quantum well by increasing the mole fraction of the outer layer. Finally, asymmetric double-layered structure is proposed. Since the targets by asymmetric double-layered structure are the retention and the sensing margin, respectively, the integrated structure can improve both performance metrics. The results are verified using the calibrated TCAD modeling and simulations.