Rough Interface Effect on High-Temperature Reliability of TSV for Electronic Packaging

The most potential three dimensional packaging method is through silicon via due to the excellent electrical performance. Nevertheless, the mismatch of CTE between SiO2 and Cu becomes the main failure form of TSV structure. In addition, the rough Cu/SiO2 interface caused by the etching process accelerates crack expansion, which reduces the high-temperature reliability of power devices. In order to investigate the failure mechanism caused by interface roughness, a novel TSV rough interface modeling method by using W-M fractal function was proposed. The reliability of TSV structure with rough interfaces under different annealing temperatures was studied. The results indicate that a high annealing temperature will contribute to greater deformation and accelerate the overflow of TSV-Cu. There is a deformation fluctuation in the rough interface area, which exacerbate the expansion of cracks. Due to the plastic deformation, with the annealing temperature increases, TSV structure tends to exhibit shear failure in the Y direction. In addition, the stress concentration caused by rough interfaces cannot be ignored, which will immensely reduce the reliability of high-power devices.