Optimized stencil opening to increase solder flowing area for solder void performance improvement

SiP (System in Package) products very often have components of various sizes due to the nature of the product requirement. Solder connection on typical 01005 to 0603 component in general exhibit very minimum solder void. However, on very large bottom pad, solder voids in BTC (Bottom terminal Component) solder joints often have challenge to meet IPC specification of 25% void max [1]. From the reliability view of the solder joint, large void area will bring inestimable risks to the solder joint. It will affect the electrical, thermal and mechanical properties of products, and even lead to product failure after customer reflow process [2]. Therefore, minimization of solder voids is very critical to improve product performance as well as to reduce product life reliability throughout its application in field.The occurrence of solder void can be related to many factors including PCB surface treatment, such as component soldering terminal condition, solder volume, solder paste selection, footprint design, stencil opening design, reflow profile, etc. There are established processes/equipment such as utilizing vacuum reflow oven can quickly improve solder void during reflow process [3], however vacuum reflow also have some shortcomings such as operational cost is significantly higher than N2 reflow. Other than cost, vacuum reflow generally has lower UPH hence creates another bottleneck in inline integrated SMT line.The study vehicle, which is a SiP LGA products with large bottom pad opening and having known of having 35% solder void observed via X-ray inspection is being utilized for optimization with the target of reducing solder void to <25% which is specification limit of IPA standard. Large bottom pad opening is required as the design of the component requires large solder joint which is unavoidable. Minimization of solder void for this large component will improve the performance of this SiP product in conjunction with its reliability significantly. From the X-ray overview of the product, it can be observed clearly that the excessive solder void is confined to this component with large bottom pad opening only but not others standard components. The challenge of this study is to maintain the existing performance of standard components yet reduce the solder void on large bottom pad. In this paper, various SMT factors been considered from stencil designs inclusive of stencil opening shape, % of stencil opening comparing to bottom pad opening, solder printing parameters to solder flowing parameter. The quality of solder paste printing for each trial is measured by 100% automatic 3D SPI (Solder Print Inspection) vision system to eliminate the potential of void is induced by inferior solder printing process. The output result of the study is based on the solder void performance inspection under x-ray and the target is to determine the best-known method to achieve minimum void rather than just to meet IPC standard. Other output attributes inclusive of solder short, tombstone, component tilting and other SMT defects is measured by AOI (Automatic Optical Inspection) to ensure improvement achieved does not create other SMT related defects. Components shear is conducted on large pad component as well as standard components to ensure connection of all components are met.