Etching scallop-less nano-TSV with F/O coupling plasma

Through-silicon via (TSV) technology is significantly important in the three-dimensional integrated circuit (3D-IC), aiming to minimize the connection distance, reduce energy consumption, and improve integration density. To increase the stacking chip layers and the mechanical reliability, it is essential to develop TSVs with the nano-scale diameters. However, the scallop pattern resulting from the Bosch etch process is fatal to nanoscale TSV. In this paper, the impact of thermal stress caused by sidewall scallop on nano-TSVs is investigated by the finite element analyses. The high stresses may lead to crack propagation and potential failures. Thus, the use of F/O coupling plasma to etch scallop-less nano-TSV is explored. The effect of etching pressure and O2/SF6 ratio on the undercut and Si etch rate is investigated in detail. The results in the study can be used to improve the reliability of nano-TSV in 3D packaging.