Numerical Study on the Correlation between Board-level Drop and Shock Tests for Chip-Scale Packages

The JEDEC-standard board-level drop test (1500 g, 0.5 ms) has been used widely to assess the performance of solder joints in IC packages. However, it still has many drawbacks, including extensive test setup, manual execution, limited real-time measurements, and lack of testability at low and high temperatures. Shock testing (i.e., low-g impact level) done using shaker systems is a promising approach to overcome these limitations, offering high test throughput and test consistency as well as the ease to integrate on-board real-time measurements and to test at varied temperatures.In this study, the relationship between drop and shock test results was investigated numerically using a quarter finite-element model of a custom-made test PCB assembled with four chip-scale packages as per JESD22B111A guidance. A factor to be considered is that the failure mode of the solder joints in the drop test should not be changed in the shock test. An approximately linear relation of maximum von Mises equivalent total stress in the critical joint between the drop (1500 g, 0.5 ms) and shock tests (150 g, 3 ms) in different solder joint array population scenarios was observed. Maximum von Mises equivalent total stress and strain-rates at critical solder joint were 50% and 80% lower, respectively, in the shock test compared to the drop test.By adjusting the pulse duration to be near to the fundamental natural frequency of the used test board, increased board bending and thus higher stress and strain-rate in solder joints would be achieved. At the same 150 g, shock at a pulse width of 1.5 ms resulted in 1.5-fold increase in stress and 2.7-fold increase in strain rates. Nonetheless, significant differences in strain dynamic between drop and shock impacts were observed, which may alter the failure mechanisms in the solder joints. Consequently, more work is needed before considering the potential replacement of drop tests with shock tests.