A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit

A 12.5-Gb/s 1/5-rate reference-less subsampling clock and data recovery (CDR) circuit is presented. The subsampling phase detection technique widely used in the low jitter phase-locked loop design is adopted for the CDR’s clock recovery operation. It brings not only a design simplification but also the low-power consumption of the CDR. The 1/5-rate subsampling phase detection circuit is also introduced for further power reduction. The false-lock detector is proposed that monotonically ascends or descends the clock frequency until the phase lock is achieved. It shares the outputs of the subsampling phase detection circuit and removes the frequency detector from the CDR loop. The measured power consumption and efficiency of the proposed CDR at 12.5 Gb/s are 8.8 mW and 0.7 pJ/bit, respectively. At the same time, the peak-to-peak and rms jitters show 21 and 3.7 ps in 2.5-GHz clock signal, respectively. The high-frequency jitter tolerance is 0.52 UIpp. The CDR including a 1-to-5 DEMUX occupies a core area of 0.087 mm2 using 65-nm CMOS process.