SEU/SET Evaluation of Digital VLSI Design from Register Transfer Level to Layout Level

As the feature size of integrated circuit (IC) continues to shrink, the soft failure probability induced by single event upset and single event transient (SEU/SET) for ICs exposing to space radiation is increasing. Since the soft failure probability is proportional to IC area, it is of great importance to study how to evaluate the sensitivity of very large scale integrated (VLSI) circuit to SEU/SET. In this paper, a generic fault injection simulation platform is designed to evaluate the responses of VLSI circuit to SEU/SET. Experiments show that the designed fault injection platform can cover the SEU/SET evaluation of VLSI design for the whole digital VLSI design flow, which includes original register transfer level design, logic gate-level netlist generated after synthesis and physical gate-level netlist generated after placement and routing. Furthermore, the proposed platform is able to extract the location information of utilized stand cells from the existing digital VLSI design flow, and carry out the simulation of single multiple bit upset and single event multiple transient (SMBU/SEMT) more accurately.