Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur

This paper presents an analog low-power sub-sampling phase locked loop (PLL) that tackles the reference spur caused by VCO load modulation from the sub-sampling operation. A complete analysis on the binary frequency shift keying (BFSK) effect including the impact of the VCO buffer is provided, followed by practical design guide that achieves the optimum spur/jitter trade-off. The proposed sub-sampling phase detector incorporates an active primary-secondary architecture for improved isolation to suppress the load modulation. The adaptive frequency locked loop (FLL) consumes zero power in the locked state and activates itself once unlocking is detected. The sub-sampling PLL is fabricated in a 40nm CMOS process. It achieves -121.5dBc/Hz phase noise at 1MHz offset frequency and an RMS jitter of 185fs integrated from 10k to 10MHz. The power dissipation is 1.14mW at 0.95V supply with a -254.1dB figure-of-merit. The proposed phase detector results in -73dBc reference spur that is among the lowest in state-of-art works.