A Fully Digital Implementation of A Reward-Modulated STDP Synapse

Reward - modulated Spike - Timing - Dependent Plasticity (R-STDP) is a learning technique for Spiking Neural Networks (SNNs) that adjusts the synaptic plasticity induced by Spike-Timing-Dependent Plasticity (STDP) using an external learning signal. This paper presents a fully digital architecture of R-STDP, and proposes, for the first time, a circuit design for the generation and modulation of the external learning signal reward. The design was validated on a Field-Programmable Gate Array(FPGA), demonstrating a power consumption of 0.205W at a frequency of 250MHz. The experimental results were consistent with the software simulation. The circuit achieves excellent tradeoffs among performance, resources, and latency. The hardware-friendly implementation of R-STDP holds the potential to facilitate SNNs on-chip learning, as well as enable applications in fields such as robotics and automatic control.