Low-Complexity Hardware Architecture of an H.264-Based Video Encoder for FPGAs

In this paper, we present an architecture for a scalable, efficient, realtime intra H.264 video encoder implemented on an FPGA. Our architecture was designed to achieve a through-put of up to 2.3 Gbit/s using a parallel and pipelined architecture described in VHDL. All modules in the architecture are optimized to utilize minimum hardware area. A parameterized encoding system and flexible architecture is proposed to provide the ability to achieve different compression ratios ranging from 1.4 to 2 with varying size and power requirements. As a baseline, with no compression, the encoder required hardware resources equivalent to 18K logic gates. This work experimented with compression ratios up to 2 which required an equivalent of 31K logic gates. The encoder performs at frequency ranges of 159–183 MHz.