The European Chips Act, The ISOLDE Project, and Open-Source Hardware

This paper summarizes the latest advancements in the European Chips Act and gives an outlook of some of the planned contributions of Silicon Austria Labs (SAL) in the research project ISOLDE. Starting from the inception of the Chips Joint Undertaking (ChipsJU), the paper will then point out recent funding activities on RISC-V for High Performance Computing (HPC) and safety critical domains in Europe, before looking more closely to the research done by Silicon Austria Labs. We will describe our current work on implementing a Post-Quantum Cryptography (PQC) co-processor, incorporating the RISC-V Instruction Set Architecture (ISA) via OpenHW group's CVA6. This co-processor and SAL's Machine Learning (ML) co-processor, would eventually be incorporated into a System-on-Chip (SoC) implementing acceleration of distributed-learning tasks via Quantum-Safe Cryptography (QSC).