FPGA Accelerated Bi-Cubic Convolution for Image Interpolation

Bi-cubic Convolution (BCC) is the extensively used image interpolation technique for data-intensive applications, such as Remote Sensing satellite optical data processing realized by performing a large number of Multiply Accumulate (MAC) operations. This paper presents a novel and efficient deeply-pipelined hardware architecture for the BCC image interpolation technique, involving streaming of input image tile-wise to reduce on-chip memory footprints and utilization of FIFOs to orchestrate the data movement between on-chip memory and the computation module (CM). Data fetching and computations are performed simultaneously, enabling double buffering and significant latency improvements. The design is implemented on an Intel Arria 10 GX 1150 FPGA attaining a frequency of 186 MHz. It achieved an overall throughput of 514 frames per second (FPS) while running on an input tile of size 256×256 with 2x scaling. The obtained computational latency is 91.39 µs, providing a speedup of 23x over CPU, 4.2x over GPU, and about 12x over existing state-of-the-art FPGA implementations.