Generation of Coverage based Verification Benchmark Programs for RISC-V Processor

The RISC-V architecture has gained significant popularity as an open and extensible instruction set architecture (ISA) for a wide range of computing applications. This paper introduces a novel approach to enhance coverage in RISC-V processor verification through the design and development of benchmark verification programs. To achieve comprehensive coverage, a CRIG (Constrained Random Instruction Generator) is designed which is capable of generating a diverse set of random instruction encodings while adhering to the RISC-V ISA specifications. enabling the creation of randomized instruction sequences based on constraints. The utilization of coverage groups ensures critical aspects of the processor are adequately tested. Through extensive testing, the paper identifies a benchmark constraint randomized file that showcases exceptional coverage, serving as a valuable reference for future verification projects. The resulting benchmark programs form a comprehensive suite that rigorously tests the RISC-V processor’s functionality, providing confidence in its compliance with the RISCV ISA specifications.