Analysis of Process Variation tolerant Low Power 10T SRAM cell for IoT applications

Designing of Low Power Static Random Access Memory (LPSRAM) cells is driven upwards by rising need of Internet of Things (IoT)-based battery-enabled electronic gadgets. In this paper 45nm technology general processing design kit (GPDK) file is used to simulate and analyze a ten transistor (10T) SRAM cell on CADENCE virtuoso tool. For varying power supply i.e. 0.5V to 1V, read and write power of 10T SRAM cell has been calculated and evaluated with other considered cells. Read power variability has been examined using Monte Carlo simulation at various voltages as well as different process corners. To minimize the access transistors conflict issue in 10T SRAM cell, authors have utilized the read decoupled structure that enhance the read operation of the cell. The simulated results are calculated and evaluated with conventional 6T SRAM cell, transistor access 8T (TA8T), data dependent power supplied (D2p11T), and 11T SRAM cell with varying supply voltages. It is very exciting to get such improved results of 10T cell dissipates 1.33×/1.21×/1.27×/1.43× less read power as compared to Conv. 6T/TA8T/D2P11T and 11T SRAM cell at 1V power supply. Furthermore, the power consumed at the time of write operation of the cell is minimized by 1.86×/2.1×/1.79×/2.07× as reference to 6T/TA8T/D2P11T and 11T SRAM cell.