System Verilog Real Number Modelling for 8-bit Flash ADC and R2R DAC

In order to rapidly test functionality using a unified top-simulated environment, modern integrated circuits (ICs) must go through pre-silicon verification methods that cover numerous analogs, mixed-mode, and digital blocks. The method of representing the behavior of an analog circuit as a signal flow model is known as real number modeling, or RNM. This indicates that each analog component’s output is a discrete sample of its inputs and internal state. To increase simulation efficiency, a behavioral Real Number Model in System Verilog for an 8-bit flash analog-to-digital converter (ADC) and an R2R digital-to-analog converter (DAC) are proposed. It is demonstrated that a comparable level of accuracy to Spice transistor-level simulation can be obtained using a pure System Verilog model.