A Gigabit Wireline Transceiver Using Time-Mode-Circuits in 28nm

This work presents a 1 Gbps serial wireline transceiver using pulse-width-modulation implemented in a 28 nm technology. The bandwidth efficiency of this time modulation is discussed and a novel system for modulation and demodulation by delay locked loops is introduced. Delay cells for the proposed architecture are designed and simulation results through all design corners are shown. The theoretical basis for design of pre- and postemphasis in the analog front end is discussed. The system consumes 13.44 mW from a 0.9 V supply voltage.