Design of 3 bit/cell NAND Memory Array Based on Ferroelectric Field Effect Transistor

Ferroelectric Field Effect Transistor (FeFET) based on HfO
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material has been actively studied in the recent times because of its small size, non-volatile memory retention and CMOS fabrication compatibility and as an alternative to NAND flash. So far only single/dual-level cell NAND array based on FeFET are reported. In this work a triple level cell (3 bit/cell) FeFET-based NAND Memory array is designed using industry standard Cadence Virtuoso circuit simulator. The operation of a 3-bit per cell FeFET memory (program-erase schemes) utilizing a 2D NAND architecture is investigated. A fast program erase speed of $1 \mu S$ of the designed FeFET based NAND array is demonstrated. The designed FeFET array has 50% more memory capacity than a dual-level cell array of same size.