Voltage Mode Charge Pump Regulator with Improved Compensation and Dynamic Body Biasing Scheme

This paper presents a switched capacitor voltage mode DC-DC Charge Pump (CP) regulator for embedded Non-Volatile Memory (NVM) application which generates 2.5V output from an input supply ranging from 1.6V to 3V and supply a maximum output current of 100 μA to the memory cell during program operation. An improved compensation technique based on capacitance multiplication is presented which helps to reduce the size of compensation capacitors while improving the stability and transient settling behaviour of CP regulator. Furthermore, differential transconductance amplifier based Dynamic Body Biasing (DBB) scheme is proposed for the discharge transistor of CP regulator. The DBB scheme helps in avoiding dead zone in supply sensing and enhances the linearity of body bias switch resistance as supply voltage varies from 1.6V to 3V. Implemented in 65nm BiCMOS process, the proposed CP regulator occupies $8322 \mu\mathrm{m} ^{2}$ area and achieves minimum 43° PM across PVT when driving highest memory size of 8Kb (200pF).