Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile

When a processor core changes its state from sleep to active, the on-chip functions at that instant are found to be quite slow at the cost of high power dissipation, which is a function of large current from power rails having colossal current ramp. This leads to the occurrence of on-chip supply noise, which has adverse influence on the chip performance. It is investigated that the use of variable frequency clock (VFC) instead of conventional clock signal can control the acceleration of switching current and subsequently the supply noise. However the prior designs to generate VFC are complex and there’s scope for improvisation, which is explored in this paper to unveil a new circuit configuration to finally examine it on ISCAS’89 and ITC’99 benchmark circuits for mitigating on-chip PSN. The 65nm UMC based new VFC design at a supply of 1.1V is tested on a floating point unit (FPU) to record a mitigation of average power and supply noise of 12.72% and 12.609% respectively with respect to an FPU driven by conventional clock.