A 0.8V, Tri-State Inverter based SRAM Cell for SoC Applications

A scalable solution to single event upsets (SEU) of Static Random Access Memory (SRAM) cells with lesser delay and power consumptions, operating at 0.8V in 14nm FinFET technology using Predictive Technology Models has been presented in this paper. The proposed designs make use of tristate inverter (TSI) based latches due to its controlling capability in the inner core of the cell and hence more robust protection to soft errors is obtained. Further, a fully digital compute in memory (CIM) multiply and accumulate unit used for bitwise multiply and accumulate operation is designed which makes use of the proposed SRAM cells, full adder circuits and 2:1 Muxes with clocked power sources which reduces the power consumed by the macro. Hence, the total power consumed by the macro was found to be $2.47 \mu \mathrm{W}$ with delay of the circuit resulting to 0.4ns.